Method and device to reduce epitaxial defects due to contact stress upon a semicondcutor wafer

ABSTRACT

A method of transferring semiconductor wafers and a semiconductor wafer support device including lift pins having a first end configured to contact a backside surface of the semiconductor wafer and at least one stress reduction feature. The stress reduction feature may be configured to reduce contact stress between the lift pins and the wafer.

BACKGROUND

In order to fabricate devices on a semiconductor wafer, a number of unitoperations (e.g., masking, etching, deposition, implanting etc.) areperformed. Semiconductor wafers may be transported from unit operationto unit operation during device fabrication. To transport thesemiconductor wafers to and from each unit operation, a storagecontainer, such as a front opening unified pod (FOUP) may be used. Arobot arm may be used to load and unload semiconductor wafers into andout of the FOUP. A transfer blade attached to an articulated robot armmay be positioned under the wafer and used to lift the wafer into andout of the FOUP. As the semiconductor wafers are delivered to a unitoperation, the articulated robot arm may raise the semiconductor waferout of the FOUP and deliver the semiconductor wafer to a chuck for theunit operation. After completion of the unit operation, the robot armloads the semiconductor wafer back into a FOUP for transport to the nextunit operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a perspective view illustrating an electrostatic chuck withwafer support lift pins extended and supporting a semiconductor wafer inaccordance with some embodiments.

FIG. 2 is a vertical cross-sectional view illustrating an electrostaticchuck with a wafer support lift pins comprising springs in accordancewith some embodiments.

FIG. 3 is a close up view illustrating the wafer support lift pins ofFIG. 2 in accordance with some embodiments.

FIG. 4A is a side view illustrating another wafer support lift pins inaccordance with some embodiments.

FIG. 4B is a vertical cross-sectional view of the illustrating a crosssection of the wafer support lift pins illustrated in FIG. 4B inaccordance with some embodiments.

FIGS. 5A-5C are side views illustrating another wafer support lift pinsin accordance with some embodiments.

FIG. 6A is a plan view illustrating a semiconductor wafer transfersystem in accordance with some embodiments.

FIG. 6B is a vertical cross-sectional view illustrating a cross sectionof the wafer transfer system of FIG. 6A along line AA′ in accordancewith some embodiments.

FIG. 7 is a horizontal cross-sectional view illustrating a cross sectionof a cluster tool with a semiconductor wafer transfer system inaccordance with some embodiments.

FIG. 8 is a flowchart illustrating a method of transferring asemiconductor wafer in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Generally, the structures and methods of the present disclosure may beused to transfer and perform unit operations on semiconductor waferswhile mitigating damage to the semiconductor wafer caused by thebackside lift pins during the loading and unloading of the wafer from anelectrostatic chuck (ESC).

As discussed above, a semiconductor wafer may be subjected to a numberof unit operations (e.g., masking, etching, deposition, implanting etc.)in order to fabricate a device on the semiconductor wafer. Semiconductorwafers may be transported from unit operation to unit operation duringdevice fabrication. To transport the semiconductor wafers to and fromeach unit operation, a storage container, such as a front openingunified (or universal) pod (FOUP) may be used. Alternatively a clustertool may allow a robotic arm to transfer the semiconductor wafer todifferent chambers of the cluster tool. Each chamber of the cluster toolmay perform a different unit operation. A robot arm may be used to loadand unload semiconductor wafers into and out of a FOUP or into and outof different chambers of the cluster tool. A transfer blade attached toan articulated robot arm may be positioned under the wafer and used tolift the semiconductor wafer. As the semiconductor wafers are deliveredto a unit operation, the articulated robot arm may deliver thesemiconductor wafer to the ESC for the unit operation. As thesemiconductor wafer is delivered to the ESC, the semiconductor wafer islowered on to lift pins of the ESC. The lift pins may be retracted, thuslowering the wafer on to the surface of the ESC. After completion of theunit operation, the lift pins may be raised to lift the semiconductorwafer off the surface of the ESC so that the articulated robot arm inorder to allow the robot arm to load the semiconductor wafer back into aFOUP for transport to the next unit operation

Each time the semiconductor wafer is lowered onto the lift pins as wellas each time the lift pins raise the semiconductor wafer off of the ESC,damage may occur to the semiconductor wafer due to the forces exerted onthe wafer by the lift pins. The damage to the semiconductor wafer maypropagate into succeeding layers deposited on the front side of thesemiconductor wafer. Subsequent epitaxial layers may be more sensitiveto wafer damage than non-epitaxial layers. For example, epitaxial layerdefects may form due to substrate lattice dislocation that occur whenthe lift pins impact the semiconductor wafer. Oxygen may be precipitateand the silicon oxide defects may form.

Moreover, subjecting the semiconductor wafer to elevated temperatures,such as used in deposition and ion implantation unit operations, mayreduce the hardness of the wafer. As a result the heated semiconductorwafer may be more susceptible to mechanical damage due to the repeatedraising and lowering performed by the ESC lift pins.

In an embodiment, the ESC is provided with lift pins that includesprings contacting the bottom end of the lift pins. When thesemiconductor wafer is loaded onto and/or lifted off the ESC through theembodiment lift pins, the springs included in the lift pins may compressand absorb some of the stress that would have been imparted on to thesemiconductor wafer. In another embodiment, the tips of the lift pinsmay be provided with an elastic cover. Similar to embodiment lift pinswith springs, the elastic cover may compress and absorb some of thestress that would have been imparted on to the semiconductor wafer. Inanother embodiment, the lifts pins may be provided with a more roundedtip than conventional lift pins. That is, rather than the tips of thelift pins ending in a point, the tips of the lift pins may include aflattened or oblate spheroid shape. In this manner, the embodiment liftpins may provide a larger contacting surface area with the backside ofthe semiconductor wafer. Such a larger contacting surface area maydistribute the forces imparted on the semiconductor wafer through theembodiment lift pins, thereby lowering the contact stress for a givencontact force.

FIG. 1 is a perspective view illustrating a semiconductor wafer supportdevice 100, such as an ESC that includes one or more stress reductionembodiments as discussed in more detail below. The stress reductionfeatures are configured to reduce contact stress imparted by the liftpins 108 onto the semiconductor wafer 110. The semiconductor wafersupport device 100 includes a base 102 which include several holes 106in its top surface 104. The lift pins 108 may be extended or retractedthrough the holes 106 in the top surface 104 of the base 102. The liftpins 108 may have an end that is configured to contact the backsidesurface 109 of a semiconductor wafer 110. As discussed in more detailbelow with reference to FIGS. 2-5C, the lift pins 108 may include asupporting pillar 107 which has a first end 107A and a second end 107B.The lift pins 108 may also include a stress-reducing element. In someembodiments, the stress-reducing element may be located at the first end107A of the supporting pillar 107 while in other embodiments, thestress-reducing element may be located at the second end 107B of thesupporting pillar 107. As discussed in more detail below with referenceto FIGS. 2-5C, the stress-reducing element may be an elastic segment ormay be integrally formed with the supporting pillar 107.

In operation, the lift pins 108 may be extended when receiving asemiconductor wafer 110. The lift pins 108 may be subsequently retractedin order to lower the semiconductor wafer 110 to the top surface 104 ofthe base 102 of the semiconductor wafer support device 100. Once thesemiconductor wafer 110 engages the top surface 104 of the base of thesemiconductor wafer support device 100, the unit operation of the devicefabrication process may be performed. After the unit operation isperformed, the semiconductor wafer 110 may be raised by the lift pins108 away from the top surface 104 of the base 102 of the semiconductorwafer support device 100 such that a transfer blade (not shown),discussed in more detail below, may be inserted to contact the backsidesurface 109 of the semiconductor wafer 110. Once the transfer bladeengages the backside surface 109 of the semiconductor wafer 110, thesemiconductor wafer 110 may be moved to the next chamber of a clustertool or to a storage box, such as a FOUP. Unit operations may include,but are not limited to masking, deposition, etching, chemical-mechanicalpolishing, ion implantation, or cleaning.

FIGS. 2 and 3 illustrate embodiment lift pins 108 that provide a stressreduction feature. As illustrated in FIGS. 2 and 3, an elastic elementsuch as a spring 112 may be disposed within the holes 106 of the base102 of the semiconductor wafer support device 100 prior to inserting thelift pins 108 in the holes 106. As discussed above, at least one liftpin 108 may include a supporting pillar 107 and an stress-reducingelement, e.g. spring 112. The supporting pillar 107 may be configured tosupport the semiconductor wafer 110. The stress-reducing element, spring112 in this embodiment, connects to the first end 107A of the supportingpillar 107 to reduce contact stress between the lift pins 108 and thesemiconductor wafer 110. In an alternative embodiment, springs 112 maybe integrally formed with the lift pin 108. In still a furtheralternative embodiment, the springs 112 may be dimensioned to insertinto a recessed cavity (not shown) formed in the first end 107 a of thesupporting pillar 107. In still another alternative embodiment, thespring 112 may be integrally formed with a bottom surface of the hole106 and configured to contact a first end 107A of the supporting pillar107 of the lift pin 108.

A semiconductor wafer 110 may be placed on the lift pins 108 (or thelift pins 108 may be used to raise the semiconductor wafer 110 off thetop surface 104 of the base 102 of the semiconductor wafer supportdevice 100). In the embodiment lift pin 108 shown in FIGS. 2 and 3, thesprings 112 may compress and thereby absorb some of the contact stressdue to weight of the semiconductor wafer 110. In an embodiment, thesprings 112 have a lateral spring constant in the range of 7-8×10³kg/mm² and a longitudinal spring constant in the range of 19-21×10³kg/mm², although greater or lesser spring constants may be used invarious embodiments of the present disclosure. The spring constant mayvary based on the material used to form the spring. Different materialsmay possess a different shear modulus value. In addition, the coiling ofthe spring 112 may impact the spring constant. The force, F, that aspring 112 may absorb may be determined by the equation:

F=−kx

where k is the spring constant and x is the spring displacement amount.

In both instances where the semiconductor wafer 110 is placed down onthe lift pins 108 or raised up off the ESC by raising the lift pins 108,the springs 112 may act as a buffer to absorb contact stress andmitigate the damage to the semiconductor wafer 110. For example, amechanical contact force that exceeds 5.1 gigapascal (GPa) may inducesemiconductor wafer 110 damage. By providing the springs 112, contactstress may be absorbed and the damage to the semiconductor wafer 110 maybe mitigated.

FIG. 4A is a side view of another embodiment lift pin 108 while FIG. 4Bis a cross-sectional view of the embodiment lift pin 18 illustrated inFIG. 4A. The embodiment lift pin 108 illustrated in FIGS. 4A and 4B mayinclude another stress reduction element. The stress-reducing element inthis embodiment includes an elastic segment, such as an elastic cover114. In these embodiments, an elastic cover 114 may be disposed over thesecond end 107B of the supporting pillar 107 of the lift pin 108. Asemiconductor wafer 110 may be placed on the elastic cover 114 of thelift pins 108 (or the lift pins 108 are used to raise the semiconductorwafer 110 off the top surface 104 of the semiconductor wafer supportdevice 100). In the embodiment lift pin 108 shown in FIGS. 4A-5C, theelastic cover 114 may compress and thereby absorb at least a portion ofthe contact stress imparted upon the semiconductor wafer 110 due toweight of the semiconductor wafer 110. In some embodiments, the materialused to form the elastic cover 114 may vary in elastic modulus in adirection perpendicular to a major axis of the lift pins 108. In anembodiment, portions of the elastic cover 114 distal to the surface thesupporting pillars 107 may have an elastic modulus greater than portionsof the elastic cover 114 proximal from the surface of the supportingpillars 107. In some embodiments, elastic cover 114 may be made of aporous material. The elastic modulus may be varied by varying the amountof porosity in the elastic cover 114, with more porosity typicallyresulting in a lower elastic modulus. In an embodiment the elasticmodulus of the elastic cover 114 may be in a range of 50-140 GPa,although materials with greater or lesser elastic modulus may be used.

The amount of contact force, i.e. the amount of force imparted to thesemiconductor wafer 110 by the lift pins 108, that may be reduced byusing the elastic cover may be determined using Equation 1.

$\begin{matrix}{{\sigma_{C}\left( {F_{N},D_{0},E_{eff}} \right)} = {0.4*\left\lbrack \frac{F_{N}E_{{eff}^{2}}}{\left( \frac{D_{0}}{2} \right)^{2}} \right\rbrack^{1/3}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

Further the effective modulus, E_(eff), may be determined using Equation2:

$\begin{matrix}{{E_{eff}\left( {E_{1},v_{1},E_{2},v_{2}} \right)} = {{2*\left( {\frac{1 - v_{1}^{2}}{E_{1}} + \frac{1 - v_{2}^{2}}{E_{2}}} \right)} - 1}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

Where F_(N): is the normal force; D₀: is the diameter of the lift pin108; E_(eff): is the effective modulus; v: is the Poisson ratio; andE_(n) is the Young's modulus of the semiconductor wafer 110 and theelastic cover 114 of the lift pins 108. The normal force F_(N) is theforce to lift the semiconductor wafer 110.

The Poisson ratio of a material is a measure of the expansion orcontraction of a material in a direction perpendicular to the directionof loading. The Young's modulus of a material is a measure of the amountof stress to cause a particular strain in a material. That is, theYoung's modulus is a measure of stiffness. The higher the Young'smodulus, the stiffer the material. The Poisson ration and the Young'smodulus are properties of the selected materials of the semiconductorwafer 110 and the elastic cover 114 of the lift pins 108.

As can be seen in Equation 1 above, the contact force a that may bereduced by various embodiment stress reduction features may be directlyproportional to the normal force F_(N) and the effective modulus E_(eff)and inversely proportion to the diameter D₀ of the lift pins 108. Thus,the contact force σ_(c) may be reduced by lowering the normal forceF_(N) and/or the effective modulus E_(eff) and/or by increasing thediameter D₀ of the lift pins 108. As can be seen in Equation 2 above,the effective modulus E_(eff) is weakly proportional, i.e. varying as(1−v²), to the Poisson ratio v₁, v₂ of the semiconductor wafer 110 andthe elastic cover 114 of the lift pins 108 and inversely proportional tothe Young's modulus E₁, E₂ of the semiconductor wafer 110 and theelastic cover 114 of the lift pins 108. Thus, a change in the Poissonratios will have a small effect on the effective modulus E_(eff) whilean increase in the Young's modulus will lower the effective modulusE_(eff).

FIGS. 5A-5C are side views of another embodiment lift pin 108. Theembodiment lift pins 108 illustrated in FIGS. 5A-5C may includeadditional stress reduction features. The stress-reducing element can beintegrally formed with the supporting pillar 107. In variousembodiments, the diameter of the supporting pillar 107 of the lift pin108 may be in the range of 2-10 mm. However, the diameter of thesupporting pillars 107 may be larger or smaller as desired.

In a first aspect illustrated in FIG. 5A, a tip 116 a disposed at thesecond end 107B of the supporting pillar 107 may be rounded/flattenedrelative to conventional lift pins. The tips 116A may be spherical inshape or slightly flattened into an oblate spheroid shape. Asillustrated in FIG. 5A, in embodiments in which the tip 116 a isessentially spherical, the spherical angle is essentially 180 degrees.Thus, the radius of curvature of such an embodiment tip 116 a may be thesame radius as the supporting pillar 107. For example, if the diameterof the supporting pillar 107 is 4 mm, the radius is 2 mm. Using a tip asshown in FIG. 5A, the radius of curvature of the tip 116 a is also 2 mmand the spherical angle is essentially 180 degrees. Thus, in such anembodiment, the radius of curvature of the tip 116 a may be the same(1:1) as the radius of the supporting pillar 107.

In a second aspect illustrated in FIG. 5B, a tip 116 b disposed at thesecond end 107B of the supporting pillar 107 may have a greaterflattening than the embodiment tip 116 a illustrated in FIG. 5A. Inembodiments as illustrated in FIG. 5B, the lift pin 108 may beconfigured with a tip 116 b that may be described as an oblate spheroidor ellipsoid in shape. For example, the radius of curvature of the tip116 b may be twice the radius of the supporting pillar 107 of the liftpin 108, resulting in a spherical angle φ of approximately 52.1 degrees.In an example lift pin 108 in which the diameter of the supportingpillar 107 is 4 mm and the radius of the supporting pillar is 2 mm, thetip 116 b as shown in FIG. 5B may have a radius of curvature of 4 mm andthe spherical angle of approximately 52.1 degrees. Thus, in such anembodiment, the radius of curvature of the tip 116 a may be twice (2:1)the radius of the supporting pillar 107.

In a third aspect illustrated in FIG. 5C, a tip 116 c disposed at thesecond end 107B of the supporting pillar 107 may have yet even a greaterflattening than the embodiment tip 116 a illustrated in FIG. 5A andembodiment tip 116 b of FIG. 5B. That is, the tips 116 c has an evenlarger spherical angle φ. In an embodiment, the radius of curvature maybe 5 times the radius of supporting pillar 107 of the lift pin 108,resulting in a spherical angle φ of approximately 24 degrees. In anexample lift pin 108 in which the diameter of the supporting pillar 107is 4 mm and the radius of the supporting pillar is 2 mm, the tip 116 cas shown in FIG. 5C may have a radius of curvature of 10 mm and thespherical angle of approximately 24 degrees. Thus, in such anembodiment, the radius of curvature of the tip 116 c may be five times(5:1) the radius of the supporting pillar 107.

In various embodiments, the radius of curvature of the tips 116 a-116 cmay be in the range of 1-5 times the radius of the supporting pillar 107of the lift pins 108. Put another way, the ratio of the radius ofcurvature of the tips 116 a-116 c as compared to the radius of thesupporting pillar 107 of the lift pins 108 may be (1:1) to (5:1).However, the radius of curvature of the tips 116 a-116 c may be largeror smaller as desired. Alternatively, the tips 116 a-116 c may bedescribed in terms of spherical angle φ. In various embodiments, thespherical angle φ of the tips 116 a-116 c may be in the range of 24-180degrees. For example, the tip may be provided with a spherical angle φin the range of 50-180 degrees. Moreover, the tip may be provided with aspherical angle φ in the range of 90-180 degrees. By providing a moreflattened pin tip 116C (i.e., smaller spherical angle φ), the surfacearea of the tip (116 a-c) disposed on the supporting pillar 107 of thelift pin 108 may be increased. The increased surface are may distributethe force imparted upon the semiconductor wafer 110 over a largersurface area, thus reducing the contact stress.

The amount of contact force that may be reduced by using the elasticcover may be determined using Equation 1, where the flattened tips 116a-116 c may vary the value of the diameter of the lift pin 108, D₀.

FIGS. 6A and 6B illustrates a semiconductor wafer processing system 200according to various embodiments. The semiconductor wafer processingsystem 200 incudes a semiconductor wafer transfer apparatus 202 whichincludes at least one articulated robot arm 204. A first end 203 of thearticulated robot art 204 includes a transfer blade 208 while a secondend 205 is rotatably connected to a housing 201. The articulated robotarm 204 may be configured so that it may rotate and translate to moreeasily transfer the semiconductor wafers 110. The transfer blade 208 maybe configured to lift and support a semiconductor wafer 110 duringtransfer of the semiconductor wafer 110 from a first FOUP 209-1 to aunit operation 210 in a semiconductor fabrication process. The unitoperation may be, but is not limited to masking, deposition, etching,chemical-mechanical polishing (CMP), ion implantation, or cleaning, etc.After performing the desired unit operation processing step, thesemiconductor wafer 110 may be removed from the unit operation by thesame or a different articulated robot arm 204. In one aspect, thesemiconductor wafer 110 may be transferred to a second FOUP 209-2. Thesecond FOUP 209-2 may be carried, by hand or mechanically via a railsystem (not shown), to the next unit operation 210. In another aspect,the semiconductor wafer processing system 200 may be part of a clustertool (not shown) that includes several unit operations 210 in a cluster.In this aspect, the semiconductor wafer transfer apparatus 202 maytransfer the semiconductor wafer 110 from one unit operation 210 to thenext unit operation 210 within the same cluster without using a FOUP.

As illustrated in FIG. 6B, a semiconductor wafer 110 supported on thetransfer blade 208 of the wafer transfer apparatus 202 may be maneuveredso that the semiconductor wafer 110 is located over the lift pins 108 ofa semiconductor wafer support device 100, such as an ESC, associatedwith the unit operation 210. The lift pins 108 may be raised to supportthe semiconductor wafer 110. Once the semiconductor wafer 110 issupported by the lift pins 108 the transfer blade 208 may be removed.The lift pins 108 may include any of the stress reduction featuresdisclosed with reference to FIGS. 2-5C. FIG. 6B illustrates, forexample, the springs 112 disposed with the lift pins 108. Thesemiconductor wafer 110 may then be lowered to the top surface 104 ofthe semiconductor wafer support device 100 (e.g., ESC).

FIG. 7 illustrates a cluster tool 220 which includes a wafer transferapparatus 202 as discussed above. As illustrated, the cluster tool 220may be configured for four unit operation chambers 210. Each unitoperation may occur in a unit operation chamber 210. However, thecluster tools 220 may be configured with more or fewer unit operationchambers 210. The cluster tool 220 may be configured with a separateinlet 222 and a separate outlet 224 so that unprocessed semiconductorwafers 110 may be provided to the cluster tool 220 via the separateinlet 222 and processed semiconductor wafers 110 may be removed from thecluster tool 220 via the separate outlet 224.

FIG. 8 is a flowchart illustrating a method 300 of transferring asemiconductor wafer 110 in accordance with some embodiments. Referringto step 302, a semiconductor wafer 110 may be lifted with a firstsemiconductor wafer support device 100. The first semiconductor wafersupport device 100 may include lift pins 108 configured to contact abackside surface 109 of the semiconductor wafer 110. At least one of thelift pins 108 includes a supporting pillar 107 configured to support thesemiconductor wafer 110. The supporting pillar 107 includes a first end107A and a second end 107B. The lift pins 108 also include astress-reducing element illustrated in FIGS. 2-5C (e.g., springs 112,elastic cover 114, rounded tips 116A, 116B, 116C) connected to either ofthe first end 107A or the second end 107B of the supporting pillar 107to reduce contact stress between the lift pins 108 and the semiconductorwafer 110. The stress-reducing element may include an elastic segment,or is integrally formed with the supporting pillar. Referring to step304, a transfer blade 208 may be maneuvered under the semiconductorwafer 110. Referring to step 306, the lift pins 108 may be lowered suchthat the semiconductor wafer 110 is supported by the transfer blade 208.Referring to step 308, the semiconductor wafer 110 may be transferredfrom a first location to a second location with the transfer blade 208.In some embodiments, the first location may be a first semiconductorprocessing unit operation 210 and the second location may be a FOUP209-2.

In some embodiments, the semiconductor wafer 110 may be transferred fromthe second location to a third location. In some embodiments, the secondlocation may be a FOUP 209-1 and the third location may be a second unitoperation 210. The method may include removing the semiconductor wafer110 from the FOUP 209-1 with the transfer blade 208, maneuvering thesemiconductor wafer 110 from the FOUP 209-1 to a second semiconductorprocessing unit operation 210 and lifting a second semiconductor wafersupport device 100 to support the semiconductor wafer 110. The secondunit operation 210 may include a second semiconductor wafer supportdevice 100 configured to support the semiconductor wafer 110. The secondsemiconductor wafer support device 100 may include second lift pins 108configured to contact a backside surface 109 of the semiconductor wafer110 and at least one second stress reduction feature illustrated inFIGS. 2-5C (e.g., springs 112, elastic cover 114, rounded tips 116 a,116 b, 116 c). The at least one second stress reduction feature may beconfigured to reduce contact stress between the second lift pins 108 andthe semiconductor wafer 110. The at least one second stress reductionfeature, similar to the first stress reduction feature, may includesprings 112 configured to contact a first end 107 a of the supportingpillar 107, an elastic cover 114 covering the first end 107A of thesupporting pillar 107, the first end 107A of the supporting pillars 107may have an oblate spheroid shape (116 a-116 c) or combinations thereof.

Generally, the structures and methods of the present disclosure can beused to transfer and perform unit operations 210 on semiconductor wafers110 while mitigating damage to the semiconductor wafer 110 caused by thelift pins 108 during loading and unloading of the semiconductor wafer110 from a semiconductor wafer support device 100, such as an ESC. Themitigation of the damage to the semiconductor wafer 110, in turn,mitigates damage propagating from the damaged semiconductor wafer intolayers deposited on the semiconductor wafer, in particular epitaxiallayers. In an embodiment, the semiconductor wafer support device 100 maybe provided with springs 112 contacting the bottom end of the supportingpillars 107. When the semiconductor wafer 110 is loaded/lifted onto thelift pins 108, the springs 112 may compress and absorb some of thestress on the semiconductor wafer 110. In another embodiment, the tipsof the lift pins 108 may be provided with an elastic cover 114. Similarto the springs 112 in the previous embodiment, the elastic cover 114 mayhave an elastic modulus that allows the elastic cover 114 to compress asthe semiconductor wafer 110 is loaded/lifted on to the lift pins 108,thereby absorbing some of the stress on the semiconductor wafer 110. Inanother embodiment, the lifts pins 108 may provide a more rounded tip116 a-116 c than conventional lift pins. That is, rather than the tipsending in a point, the tips of the supporting pillars of the lift pins108 may have a flattened or oblate spheroid shape 116 a-116 c. In thismanner, the lift pins 108 may provide a larger contacting surface areawith the backside of the semiconductor wafer 110. The larger contactingsurface are may distribute the force imparted upon the semiconductorwafer 110 over a greater surface area, thereby lowering the contactstress for a given contact force.

An embodiment is drawn to a semiconductor wafer support device 100including lift pins 108 configured to contact a backside surface 109 ofa semiconductor wafer 110. At least one of the lift pins 108 includes asupporting pillar 107 configured to support the semiconductor wafer 110.The supporting pillar 107 includes a first end 107A and a second end107B. The semiconductor wafer support device 100 also includes astress-reducing element (e.g., springs 112, elastic cover 114, roundedtips 116A, 116B, 116C) connected either of the first end 107A or thesecond end 107B of the supporting pillar 107 to reduce contact stressbetween the lift pins 108 and the semiconductor wafer 110. Thestress-reducing element may include an elastic segment (e.g., springs112, elastic cover 114) or is integrally formed with the supportingpillar (e.g., rounded tips 116A, 116B, 116C).

Another embodiment is drawn to a semiconductor wafer processing system200 including an articulated robot arm 204 having a first end and asecond end, a transfer blade 208 located at the first end of thearticulated robot arm 204 and a semiconductor processing unit operation210 comprising a semiconductor wafer support device 100. Thesemiconductor wafer support device 100 may include lift pins 108configured to contact a backside surface 109 of a semiconductor wafer110. At least one of the lift pins 108 includes a supporting pillar 107configured to support the semiconductor wafer 110. The supporting pillar107 includes a first end 107A and a second end 107B. The semiconductorwafer support device 100 also includes a stress-reducing element (e.g.,springs 112, elastic cover 114, rounded tips 116A, 116B, 116C) connectedeither of the first end 107A or the second 107B of the supporting pillar107 to reduce contact stress between the lift pins 108 and thesemiconductor wafer 110. The stress-reducing element may include anelastic segment (e.g., springs 112, elastic cover 114) or is integrallyformed with the supporting pillar (e.g., rounded tips 116A, 116B, 116C).

Another embodiment is drawn to a method 300 of transferring asemiconductor wafer 110 including lifting the semiconductor wafer 110with a first semiconductor wafer support device 100. A semiconductorwafer 110 may be lifted with a first semiconductor wafer support device100. The first semiconductor wafer support device 100 may include liftpins 108 configured to contact a backside surface 109 of thesemiconductor wafer 110. At least one of the lift pins 108 includes asupporting pillar 107 configured to support the semiconductor wafer 110.The supporting pillar 107 includes a first end 107A and a second end107B. The lift pins 108 also include a stress-reducing elementillustrated in FIGS. 2-5C (e.g., springs 112, elastic cover 114, roundedtips 116A, 116B, 116C) connected to either of the first end 107A or thesecond end 107B of the supporting pillar 107 to reduce contact stressbetween the lift pins 108 and the semiconductor wafer 110. Thestress-reducing element may include an elastic segment, or is integrallyformed with the supporting pillar. A transfer blade 208 may bemaneuvered under the semiconductor wafer 110. The lift pins 108 may belowered such that the semiconductor wafer 110 is supported by thetransfer blade 208. Referring to step 308, the semiconductor wafer 110may be transferred from a first location to a second location with thetransfer blade 208.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor wafer support device comprising:lift pins configured to contact a backside surface of a semiconductorwafer, at least one of the lift pins comprising: a supporting pillarconfigured to support the semiconductor wafer, the supporting pillarcomprising a first end and a second end; and a stress-reducing elementconnected either of the first end or the second of the supporting pillarto reduce contact stress between the lift pins and the semiconductorwafer, wherein the stress-reducing element comprises an elastic segment.2. The semiconductor wafer support device of claim 1, wherein theelastic segment comprises a spring configured to contact the first endof the supporting pillar, wherein the second end of the supportingpillar contacts the backside of the semiconductor wafer, wherein thespring is integrally formed with the supporting pillar and configured toabsorb at least a portion of a contact stress between the lift pin andthe semiconductor wafer.
 3. The semiconductor wafer support device ofclaim 2, wherein the spring has a lateral spring constant in a range of7-8×10³ kg/mm² and a longitudinal spring constant in a range of19-21×10³ kg/mm².
 4. The semiconductor wafer support device of claim 1,wherein the elastic segment comprises an elastic cover covering thesecond end of the supporting pillar, wherein the elastic cover absorbsat least a portion of the contact stress between the lift pin and thesemiconductor wafer.
 5. The semiconductor wafer support device of claim4, wherein the elastic cover varies in elastic modulus in a directionperpendicular to a major axis of the lift pins.
 6. The semiconductorwafer support device of claim 4, wherein the elastic cover comprises aporous material.
 7. The semiconductor wafer support device of claim 1,wherein the stress-reducing element integrally formed with thesupporting pillar comprises the second of the supporting pillar havingan oblate spheroid shape, wherein a radius of curvature of the stressreducing element may be in a range of 1-5 times a radius of thesupporting pillar.
 8. The semiconductor wafer support device of claim 1,wherein the semiconductor wafer support device comprises anelectrostatic chuck comprising: a base configured to support thesemiconductor wafer; and holes in the base, wherein the lift pins arelocated in the holes and are configured to lift the semiconductor waferoff the base and lower the semiconductor wafer on to the base.
 9. Asemiconductor wafer processing system comprising: an articulated robotarm having a first end and a second end; a transfer blade located at thefirst end of the articulated robot arm; and a semiconductor processingunit operation comprising a semiconductor wafer support device, thesemiconductor wafer support device comprising: lift pins configured tocontact a backside surface of a semiconductor wafer, at least one of thelift pins comprising: a supporting pillar configured to support thesemiconductor wafer, the supporting pillar comprising a first end and asecond end; and a stress-reducing element connected either of the firstend or the second of the supporting pillar to reduce contact stressbetween the lift pins and the semiconductor wafer, wherein thestress-reducing element comprises an elastic segment.
 10. Thesemiconductor wafer processing system of claim 9, wherein the at leastone stress reduction feature comprises: a spring to contact the firstend of the supporting pillar, wherein the second end of the supportingpillar contacts the backside of the semiconductor wafer, wherein thespring is configured to absorb at least a portion of a contact stressbetween the lift pin and the semiconductor wafer; or an elastic covercovering the second end of the supporting pillar, wherein the elasticcover absorbs at least a portion of the contact stress between the liftpin and the semiconductor wafer; or the first end of the supportingpillar having an oblate spheroid shape; or a combination thereof. 11.The wafer processing system of claim 10, wherein the articulated robotarm is configured to rotate and translate.
 12. The semiconductor waferprocessing system of claim 11, wherein the semiconductor waferprocessing system comprises a cluster tool.
 13. A method of transferringa semiconductor wafer comprising: lifting the semiconductor wafer with afirst semiconductor wafer support device, the first semiconductor wafersupport device comprising: lift pins configured to contact a backsidesurface of the semiconductor wafer, at least one of the lift pinscomprising: a supporting pillar configured to support the semiconductorwafer, the supporting pillar comprising a first end and a second end;and a stress-reducing element connected to either of the first end orthe second end of the supporting pillar to reduce contact stress betweenthe lift pins and the semiconductor wafer, wherein the stress-reducingelement comprises an elastic segment; maneuvering a transfer blade underthe semiconductor wafer; lowering the lift pins of the firstsemiconductor wafer support device such that the semiconductor wafer issupported by the transfer blade; and transferring the semiconductorwafer from a first location to a second location with the transferblade.
 14. The method of claim 13, further comprising absorbing thecontact stress by compressing springs contacting a first end of thesupporting pillar.
 15. The method of claim 13, further comprisingabsorbing the contact stress by compressing an elastic cover covering asecond end of the supporting pillar.
 16. The method of claim 13, whereinlifting the semiconductor wafer with the first semiconductor wafersupport device comprises contacting the semiconductor wafer with liftpins having an oblate spheroid shape located at a first end of the liftpins.
 17. The method of claim 13, wherein the first location comprises afirst semiconductor processing unit operation and the second locationcomprises a front opening unified pod (FOUP).
 18. The method of claim17, further comprising transferring the semiconductor wafer from thesecond location to a third location by: removing the semiconductor waferfrom the FOUP with the transfer blade; maneuvering the semiconductorwafer from the FOUP to a second semiconductor processing unit operation;and lifting a second semiconductor wafer support device to support thesemiconductor wafer, the second semiconductor wafer support devicecomprising: second lift pins comprising: a supporting pillar configuredto support the semiconductor wafer, the supporting pillar comprising afirst end and a second end; and at least one stress-reducing elementconnected either of the first end or the second of the supporting pillarto reduce contact stress between the lift pins and the semiconductorwafer, wherein the stress-reducing element comprises an elastic segment.19. The method of claim 18, wherein the at least one second stressreduction feature comprises: a spring configured to contact thesupporting pillar, wherein the spring is integrally formed with thesupporting pillar and configured to absorb at least a portion of acontact stress between the first end of the lift pin and thesemiconductor wafer; or an elastic cover covering the second end of thesupporting pillar, wherein the elastic cover absorbs at least a portionof the contact stress between the lift pin and the semiconductor wafer;or the first end of the supporting pillars having an oblate spheroidshape; or a combination thereof.
 20. The method of claim 17, wherein thefirst semiconductor processing unit operation is configured to performone of masking, deposition, etching, chemical-mechanical polishing(CMP), ion implantation, or cleaning.